Magnetic MRAM memories have met with renewed interest following the development of magnetic tunnel junctions having a high magnetoresistance at ambient temperature. These magnetic random access memories have indeed many advantages:                a speed comparable with that of static random access memories (SRAM),        non volatility, as in flash memories,        absence of reading and writing degradation over time,        insensitivity to ionizing radiations.        
They are hence capable of replacing memories with a more traditional technology (DRAM, SRAM, flash) and thus of becoming a universal memory.
The first architectures of magnetic memories are constituted of a set of memory points or memory cells, each constituted of an element said to be with “giant magnetoresistive effect”, constituted of a stack of several metallic layers alternatively magnetic and non magnetic.
This type of structure has for example been described in documents U.S. Pat. No. 4,949,039 and U.S. Pat. No. 5,159,513 for the basic structure and in document U.S. Pat. No. 5,343,422 for making a RAM memory from such basic structures.
This technology, thanks to its architecture, enables non-volatile memories to be made with a simple technology, albeit of limited capacity. The fact that the memory elements or points are connected serially along each line limits the possibility of integration, since the signal gets weaker and weaker as the number of memory elements or points increases.
The development of memory points with magnetic tunnel junction has made possible a significant increase in the performance and mode of operation of such memories. Such magnetic memories with magnetic tunnel junction have for example been described in document U.S. Pat. No. 5,640,343. In their simplest form, they are composed of two magnetic layers with different switching fields, magnetically decoupled with a thin insulation layer, called tunnel barrier. When the magnetization of the storage resp. reference layers constituting the two aforementioned magnetic layers and located on each side of the tunnel barrier are anti-parallel, the resistance of the magnetic tunnel junction is high. Conversely, when the magnetizations are parallel, this resistance becomes low.
The most classical architecture, called FIMS (acronym for Field Induced Magnetic Switching), i.e. the reversing of the magnetization by an external magnetic field, created by current or conductor lines associated to each of said magnetic points, is the one described in document U.S. Pat. No. 6,021,065 and in the publication “Journal of Applied Physics” vol. 81, 1997, page 3758 and represented in FIG. 1.
Each memory element or point 10 is constituted by the association of a transistor of CMOS technology 12 and of a magnetic tunnel junction MTJ 11. Said tunnel junction 11 comprises at least one magnetic layer 20, called “storage layer”, one thin insulation layer 21 and one magnetic layer 22 called “reference layer”.
Preferably, the two magnetic layers 20 and 21 are made from 3d metals (Fe, Co, Ni) and their alloys (capable of containing boron or zirconium so as to render the structure of said layers amorphous and to flatten their interfaces), and the insulation layer 21 is traditionally constituted of amorphous alumina (AlOx) or of crystalline or textured magnesium oxide (MgO).
Advantageously, the reference layer can itself be constituted of a stack of several layers, such as described for example in document U.S. Pat. No. 5,583,725, in order to constitute a synthetic antiferromagnetic layer (SAF). In the same way, it is possible to replace, for each of the memory points, the single magnetic tunnel junction by a double magnetic tunnel junction, such as described for example in publication Y. Saito & al, Journal of Magnetism and Magnetic Materials, Volume 223, 2001, page 293. In this case, the storage layer is provided between two insulation layers, with the structure comprising two reference layers placed on the sides opposite said respective insulation layers.
The magnetic field pulses produced by having short electric pulses, typically of 2 to 50 nanoseconds and of an intensity on the order of several milliamperes, circulate in the current lines 14 and 15, ensure the writing selectivity of the memory point localized at the intersection of these current lines. The intensity of these pulses and their synchronization are indeed adjusted so that only the magnetization of the memory point located at the intersection of these two current lines is capable of switching.
Due to the writing mechanism of these memory points, it is possible to understand the limitations of this architecture:                Inasmuch as the writing is ensured by an external magnetic field, it is subject to the value of the individual switching field of each memory point. As the distribution function of the switching fields for all of the memory points is wide (it is indeed not uniform because of manufacturing constraints and intrinsic statistical fluctuations), it is necessary that the magnetic field on the selected memory point be greater than the highest distribution switching field, with the risk of accidentally reversing certain memory points located on the corresponding line or column, where the switching field located in the lower part of the distribution is weaker than the magnetic field generated by the line or column alone.        Furthermore, considering that in general, the average value of the switching field increases when the size of the memory points diminishes, which one strives to achieve for reasons of space and cost, an ever higher current is expected in future product generations. Therefore, the electric power required for operating these memories will be all the greater as integration becomes more and more advanced.        Finally, the stability of the magnetization of the free layer with respect to heat fluctuations is no longer guaranteed when the size of the memory point diminishes. Indeed, the energy barrier that needs to be overcome to make the magnetization of this layer switch from one orientation to the other is proportional to this layer's volume. When the volume decreases, the height of this barrier then becomes comparable to the thermal agitation. The information written into the memory is then no longer maintained. To remedy this difficulty, it is necessary to increase the magnetic anisotropy of the free layer by selecting a material with a stronger anisotropy or by increasing the shape anisotropy of the memory point, for example. By doing this, however, the magnetic field necessary for the magnetic switching increases, which results in an increased electric consumption for generating the field necessary to the magnetic switching.        
Also, in order to overcome this difficulty, we have suggested using thermally-assisted magnetic random access memories, designated by the acronym TA-MRAM. The particularity of the memory point stacking in this architecture is the pinning of the storage layer by an antiferromagnetic layer with a critical temperature lower than that of the second antiferromagnetic layer pinning the reference layer. This technique is for example described in document U.S. Pat. No. 6,385,082.
In this configuration, selectivity to writing is achieved by a short increase of the temperature of the first memory addressed, achieved by a current pulse going through said considered memory point. To write the point, this temperature increase is then combined either with a magnetic field pulse, or with the spin transfer phenomenon achieved by injecting a spin polarized current through the storage layer of said memory point.
The typical stacking of a characteristic memory point for thermally-assisted magnetic random access memories TA-MRAM is represented in FIG. 2. In this stacking of the magnetic tunnel junction 31, the storage layer 40 is pinned by an antiferromagnetic layer 41. In the same manner as in the case of FIMS memories, an insulation layer 42 is comprised between the storage layer 40 and the reference layer 43. According to this configuration, the two magnetic layers are advantageously made in 3d transition metals (Fe, Co, Ni) and their alloys, preferably doped (with boron or zirconium notably), and the insulation layer can be alumina or magnesium oxide. In an advantageous embodiment, the magnetic reference layer 43 is coupled with an antiferromagnetic layer 44 whose function is to block the layer 43 so that its magnetization does not switch during writing. The critical temperature of the antiferromagnetic layer 44 pinning the reference layer 43 is much greater than the critical temperature of the antiferromagnetic layer 41 pinning the storage layer 40.
Here again, the magnetic reference layer 43 can be a synthetic antiferromagnetic layer constituted of several layers.
According to this embodiment, the antiferromagnetic layer 41 has a so-called “critical” final temperature BT above which the stabilizing so-called “exchange” magnetic field it exerts on the free layer 40 is no longer effective on the storage layer 40. The material making up the antiferromagnetic layer 41 as well as its thickness are selected so that the critical temperature BT is greater than the temperature of use of the memory (idle operating temperature). In the same manner, the critical temperature BT of the antiferromagnetic layer 44 adjacent to the pinned layer 43 is selected to be greater than and quite distant from the critical temperature of the antiferromagnetic layer 41.
This particular architecture has two or three levels of current lines depending on whether the switching is achieved by spin transfer or by magnetic field. First, for writing by magnetic field, a current line 30 called “field line” is located under the magnetic tunnel junction 31 without being in contact with the latter. This line is designed to generate the magnetic field necessary for reversing the storage layer 40 as soon as an electric current of several milliamperes goes through it and generates a temperature rise exceeding the critical temperature of the antiferromagnetic layer 41 pinning the storage layer 40. This line does not exist when the switching is achieved by injection of a spin-polarized current. Secondly, another current line 32 called “bit line” is located above the magnetic tunnel junction 31 of the memory point considered and in contact with it. Finally, a third current line 33 called “word line” is in contact, through a via 34, with a CMOS (complementary metal oxide semiconductor) transistor 35 whose “word line” constitutes the grid. In the same way as for the FIMS architecture, in a TA-MRAM architecture the “word line” controls the opening or closing of the transistors' channel over its entire length by applying or not a threshold voltage, with each of the transistors operating in switch mode for each of the associated memory points.
In writing mode, the CMOS transistor 35 of the memory point to be written is closed by applying an adequate voltage in the “word line” 33. A heating current is then sent in the memory point to be written by the “bit line” 32. Above a certain density of the current, the latter induces a temperature rise of the magnetic tunnel junction 31 beyond the critical temperature of the antiferromagnetic layer 41. The exchange field stabilizing the free layer 40 then becomes zero and said storage layer can be written at very reduced fields. To write the storage layer 40, an electric pulse is then sent into the field line 30 once the critical temperature has been reached (after several nanoseconds). This pulse generates a sufficient magnetic field to return the magnetization of the storage layer 40 to the desired direction (writing of the bit “1” or “0”). For a switching by injection of spin polarized current, the heating current is used both for heating the storage layer of the memory point and for applying a spin transfer torque onto the magnetization of this layer. To this effect, the flow of electrons of the heating current must be spin polarized, which is generally achieved by having it go through an additional magnetic field called polarization layer—in the case of the stack of FIG. 2, this role is played by the reference layer. Once the storage layer 40 has been written, the heating current is then cut in the magnetic tunnel junction 31 (by cutting the current in the “bit line” 32 and opening the transistor 35). The global temperature of the memory point then falls very rapidly (several nanoseconds) below the critical temperature of the antiferromagnetic layer 41 (typically to the idle operating temperature) and the exchange field reverts to its initial value but in opposite direction, stabilizing again the storage layer 40.
Such magnetic memories with thermally-assisted writing have a number of advantages, among which can be mentioned:                a significant improvement in the writing selectivity due to the fact that only the memory point to be written is heated;        the maintaining of the information written in the memory even when the memory point is exposed to parasite magnetic fields at ambient temperature;        an improvement of the thermal stability of the information by using materials with a strong magnetic anisotropy at ambient temperature (intrinsic or due to the exchange anisotropy field of the antiferromagnetic layer pinning the storage layer 40);        the possibility of reducing significantly the size of the memory point cells without affecting their stability limit by using materials with a strong magnetic anisotropy at ambient temperature or with a storage layer pinned by exchange anisotropy;        a reduction of the consumption during writing;        the possibility of obtaining multi-level storage cells in certain circumstances.        
Despite these advantages, there are however some difficulties in terms of manufacturing technology.
The main difficulty is linked to the need to apply a current pulse through the magnetic tunnel junction in order to heat the memory point to a temperature greater than the critical temperature of the antiferromagnetic layer pinning the storage layer. This current pulse is liable to subject the ultra-thin oxide layer constituting the tunnel barrier to a considerable electric stress. The associated voltage could indeed reach or even exceed, in systems not adapted from the point of view of thermal confinement, the breakdown voltage of such an oxide layer, which is typically around 1 Volt. Furthermore, even if the voltage applied onto the tunnel barrier is lower than its breakdown voltage, the stress linked to the electric current pulse can result in considerable aging effects in the long term, notably after a great number of writing cycles.
Document US2006120126 discloses a magnetic junction having a first and a second ferromagnetic layer having each a magnetization pinned in an essentially opposite direction, and a free third ferromagnetic layer placed between the first and second layers. The junction also comprises two resistive intermediary layers, one between the first and third ferromagnetic layer and the other between the second and third ferromagnetic layer. The presence of intermediary layers makes it possible to lower the magnitude of critical current required for reversing the magnetic field of the free ferromagnetic layer.
In document US2005254287, a magnetic junction comprises a blocked ferromagnetic layer and a free ferromagnetic layer written by spin transfer, the two layers being separated by layer having a confined current path. The junction also comprises an additional spin barrier layer and/or spin accumulation layer, the free layer being located between the layer having a confined current path and the spin barrier layer and the additional layer. The latter allows the efficiency of the spin injection to be increased when the magnetization is reversed by spin transfer.
A weaker spin current for reversing the magnetization is also achieved with the junction described in document WO2007025050 and having an insulation layer, located between a pinned ferromagnetic layer and a free ferromagnetic layer, as well as a spin accumulation layer located adjacent to the free layer and allowing a greater magnetoresistance of the junction.
Similarly, the magnetic junction described in document U.S. Pat. No. 6,958,927 allows a weaker spin current to be used for writing the free ferromagnetic layer thanks to the presence of a semimetal layer on the surface of the reference layer.
In order to simultaneously maintain a sufficient considerable current injected through the memory point whilst minimizing the voltage at the terminals of the oxide layer constituting the tunnel barrier, it has been proposed in the past to use a double tunnel junction, i.e. two magnetic tunnel junctions separated from one another by a metallic layer, such as described for example in document U.S. Pat. No. 6,950,335. By doing this, for the same power density, which constitutes the critical memory-point heating parameter, one achieves a considerable diminution of the voltage at the terminals of each of the tunnel barriers. However, this double magnetic tunnel junction has an increased complexity as regards the making of the stack and of the memory cells, notably during the burning phase of the memory point.
Furthermore, using a double magnetic tunnel junction has disadvantages for an architecture of writing based on spin transfer. Indeed, if the magnetizations of the two magnetic reference layers are blocked in anti-parallel fashion, the efficiency of the spin torque is considerable but the value of the resistances of the two memory states becomes comparable and, subsequently, the reading margin finds itself drastically reduced.
Alternatively, if the magnetizations of the two magnetic reference layers are blocked in parallel, the reading margin is considerable but the efficiency of the spin torque is significantly reduced inasmuch as the two contributions for both reference layers are subtracted from one another.